The art of computer simulation or verification of electrical designs is well established. A computer model of a logic circuit design is created based on integrated circuit (IC) models and their interconnections. This logic circuit design model is then stimulated with signals emulating signals applied to a real printed circuit board, built according to the aforementioned electrical design.
Because of high processing speed requirement, the computer aided engineering (CAE) software that simulates electrical designs is usually operating on engineering workstations such as SUN or Apollo. However, even these high power and expensive workstations cannot efficiently handle designs in excess of 40,000 to 50,000 gates or cells. Since today's gate array technologies allow for manufacturing of an IC having in excess of 100,000 cells and printed circuit boards having in excess of 200,000 gates, a new method of efficient electrical design simulation is needed.
The major problem with present simulators is their incompatiblity with the design process. Every design is developed in sections or small design increments. If there is any design problem then designer is locating and reviewing only the design problem area. Unfortunately, the present logic simulators simulate electrical logic designs in their entirely and they cannot by their design exclusively simulate a selected design section. Even if designer is currently working on a small design section, the designer must simulate the entire design which consumes a lot of computer time.
In the last few years the electrical logic designs, such as gate arrays, have became so complex that to have control over the design performance, each design section has to be simulated as it is being developed. Since all present electrical simulators simulate the entire design, they operate slowly and are difficult to use. The present invention solves the simulation bottleneck by allowing simulation of selective logic design sections. Moreover, these logic design sections can be selected and simulated instantly, without any visible loss of time on compilations.
The present simulators compile designs in a batch mode. This means that every, even minute, design change, has to be compiled together with the entire design for tens of minutes before the designer can simulate the design change. None of the batch compilers is capable of compiling exclusively design changes.
The signals that stimulate electrical logic designs are called test vectors. To exercise a design properly, the designer must very often modify the test vectors to find all combinations of input and output conditions that are needed for complete design validation. Unfortunately, such test vectors changes are cumbersome and time consuming with present simulators because each test vector change is subject to lengthy batch compilation together with the entire design.
The printed circuit boards have became so complex that testing them requires a lot of specialized test equipment and trained personnel to manage the sophisticated test equipment. The use of simulation tools for printed circuit board testing has not been very succesful because these simulators simulate the entire board design and therefore they are unduly slow in operation.
It is therefore one object of this invention to provide a new system and method for high speed simulation of electrical logic designs by allowing selective simulation of design sections.
Another objective of this invention is to provide an electrical simulation environment based on an incremental compiler that instantly registers all design changes and eliminates a need for lengthy batch compilations of the design changes. It is also an object of the present invention to eliminate lengthy compilations of test vector modifications by using a new incremental compiler.
Still another objective of this invention is to provide a low cost and high speed system and method for testing of selective printed circuit board sections.